Apparatus, system, and method for digital modulation of power amplifier in polar transmitter

ABSTRACT

An amplifier receives an amplitude signal of a polar modulated signal at a base or gate terminal of a transistor and receives a phase modulated carrier signal of the polar modulated signal at the base or gate terminal of the transistor. The amplifier combines the amplitude signal and the phase modulated signal to produce a full complex waveform at a collector or drain terminal of the transistor.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation-in-part application of U.S. application Ser. No.11/315,090, filed on Dec. 22, 2005, which is incorporated herein byreference in its entirety.

BACKGROUND

There are many benefits to using polar modulation as a means oftransmitting information. Polar modulation makes possible theapplication of the amplitude modulation data signal at the very laststage of a transmitter before an antenna. As a result, all previousamplification stages may be operated in a constant envelope mode and canthus be biased very efficiently. Polar modulation also makes it possibleto reduce the current drain quickly as the transmit power is reduced.Polar modulation provides clear talk-time benefits for wireless handsetapplications.

A common technique used to amplitude modulate a power amplifier includesmodulating the power amplifier supply voltage. In the context of a poweramplifier based on Gallium Arsenide (GaAs) heterojunction bipolartransistor (HBT) technology, amplitude modulation may be achieved bymodulating the collector voltage applied to a HBT device (e.g.,transistor) at the output stage of the power amplifier. Typically, thecollector voltage may be modulated by introducing a metal oxidesemiconductor (MOS) device in series with the power supply (e.g., thebattery), which delivers the required current at a controlled voltage tothe collector of the HBT device. The voltage drop across the MOS device,however, degrades the optimum efficiency that can be achieved relativeto the situation with no MOS device. An additional drawback of the MOSdevice approach is that the modulation bandwidth that can be supportedis limited by the both the capacitive loading associated with the largeMOS device, and also by the closed-loop that is typically required toovercome the non-linear characteristic of the MOS device. Accordingly,there is a need for an alternate technique for amplitude modulation.

SUMMARY

In one embodiment, an apparatus comprises an amplifier to receive anamplitude signal of a polar modulated signal at a gate terminal of atransistor. The amplifier receives a phase modulated carrier signal ofthe polar modulated signal at the gate terminal of the transistor. Theamplifier combines the amplitude signal and the phase modulated signalto produce a full complex waveform at a drain terminal of thetransistor.

In one embodiment, an apparatus comprises a first amplifier to receive afirst amplitude signal of a polar modulated signal at a gate terminal ofa first transistor, to receive a first phase modulated carrier signal ofthe polar modulated signal at the gate terminal of the first transistor,and to combine the first amplitude signal and the first phase modulatedsignal to produce a first full complex waveform at a drain terminal ofthe first transistor.

In one embodiment, a system comprises a first antenna and a firstamplifier coupled to the first antenna. The first amplifier to receive afirst amplitude signal of a polar modulated signal at a gate terminal ofa first transistor, to receive a first phase modulated carrier signal ofthe polar modulated signal at the gate terminal of the first transistor,and to combine the first amplitude signal and the first phase modulatedsignal to produce a first full complex waveform at a drain terminal ofthe first transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one embodiment of a polar modulated transmittercomprising a digital segmented power amplifier.

FIG. 2 illustrates one embodiment of a polar modulated transmittercomprising a power amplifier controlled using a suitable digital basemodulation technique.

FIG. 3 illustrates one embodiment of a polar modulated transmittercomprising power amplifier controlled using a suitable digital basemodulation technique.

FIG. 4 illustrates one embodiment of a polar transmitter.

FIG. 5 illustrates one embodiment of a polar modulated transmittercomprising one embodiment of power amplifier and driver circuit toprovide bias currents and voltages to power amplifier.

FIG. 6 illustrates one embodiment of a multi-mode polar transmitter.

FIG. 7A illustrates one embodiment of a bias interface circuit for firstand second amplification stages of respective power amplifiers.

FIG. 7B illustrates one embodiment of a bias interface circuit for thirdamplification stages of respective power amplifiers.

FIG. 8 illustrates a graph of a transfer characteristic of measuredAM-AM and AM-PM at high power without digital correction.

FIG. 9 illustrates one embodiment of a logic flow diagram.

FIG. 10A illustrates one embodiment of a bias interface circuit forfirst and second amplification stages of respective power amplifiers.

FIG. 10B illustrates one embodiment of a bias interface circuit forthird amplification stages of respective power amplifiers.

DETAILED DESCRIPTION

In one embodiment, a technique to amplitude modulate a polar transmittercomprises modulating a transistor at the output stage of a poweramplifier via a base terminal of the transistor rather than a collectorterminal. In one embodiment, the amplifier transistor may be formed ofGaAs HBT technology, for example. In a base modulation controltechnique, an MOS device may be provided in series with a base terminalof the output transistor rather than the collector terminal. Therefore,the voltage drop across the MOS device is eliminated and the efficiencyperformance of the transmitter may be improved. Furthermore, theintrinsic baseband to radio frequency (RF) transfer characteristicsassociated base modulation may exhibit linearity characteristics thatmay be processed using any suitable pre-distortion or correctiontechnique. The embodiments are not limited in this context.

In one embodiment, digital polar modulation techniques may comprise ahigh degree of digital content relative to analog polar modulationtechniques. For example, a digital amplitude modulator may beimplemented as a digital segmented power amplifier. Embodiments ofdigital segmented power amplifiers (also known as a radio frequencydigital-to-analog converters or RFDACs) are discussed in commonly ownedand commonly assigned United States Patent Application PublicationNumbers US 2004/0247040, and US 2004/0247047, which are incorporatedherein by reference. A digital segmented power amplifier may becontrolled such that the digital envelope may be corrected inconjunction with digital phase correction techniques associated with adigital phase modulator. Embodiments of such digital envelope correctiontechniques are discussed in commonly owned and commonly assigned UnitedStates Patent Application Publication Number US 2004/0183635, which isincorporated herein by reference.

In one embodiment, digital processing techniques discussed herein may becombined with any suitable analog and/or digital circuits to obtainmodulation across multiple modulation techniques. These modulationtechniques may include, for example, Gaussian Mean Shift Keying (GMSK)used in GSM, Gaussian Frequency Shift Keying (GFSK) used in DigitalEuropean Cordless Telecommunications (DECT) and Bluetooth, Phase ShiftKeying with eight states allowing for coding using 8-bit combinations(8-PSK) used in EDGE, Offset Quadrature Phase Shift Keying (OQPSK) andHybrid Phase-Shift Keying (HPSK) used in IS-2000, π/4 DifferentialQuadrature Phase-Shift Keying (DQPSK) used in Time Division MultipleAccess (TDMA) and Orthogonal Frequency Division Modulation (OFDM) usedin 802.11 and the like, among others. The embodiments are not limited inthis context.

FIG. 1 illustrates one embodiment of a polar modulated transmitter 100comprising a digital segmented power amplifier 128. Polar modulatedtransmitter 100 comprises digital correction and processing modules.These modules may be configured to render the various embodimentsdiscussed herein suitable for complementary metal oxide semiconductor(CMOS) technology scaling. The digital correction and processing modulesmay be configured to convert input binary data into vector modulation ofan RF carrier. In various embodiments, the vectors may be representedeither in rectangular coordinate form in terms of an in-phase (I)component and a quadrature component (Q) or may be represented in polarform in terms of magnitude (R) and phase angle (θ). The I and Qcomponents may be converted to polar components R and θ using anysuitable technique including, but not limited to, a CORDIC algorithm.The polar amplitude R and phase θ components may be pre-distorted in apiecewise linear manner to compensate for non-linearity or distortionintroduced into output signal 130 by power amplifier 128. The relativetiming of the R and θ paths also may be individually adjusted tocompensate for delays introduced by the various circuit elements. Theinput data also may be processed by pulse shaping filters. Theembodiments, however, are not limited in this context.

Data 102 is received at polar processing module 104. In one embodiment,data 102 may comprise rectangular signal coordinates (e.g., I, Q) to bereceived and converted to polar signal coordinates (e.g., R, θ) by polarprocessing module 104. In one embodiment, polar processing module 104may be implemented using any suitable conversion techniques, including aCORDIC algorithm. In one embodiment, polar processing module 104converts input data 102 from rectangular coordinates (I, Q) to polarcoordinates (R, θ) and produces output signals comprising an amplitudecomponent 106 (e.g., R) and a phase component 108 (e.g., θ). Amplitudecomponent 106 and phase component 108 may be processed in separatepaths. The embodiments are not limited in this context.

Amplitude component 106 may be provided to amplitude correction module110. Amplitude component 106 may be provided in digital form comprising2-N bits, where N represents any suitable number of bits to representamplitude component 106 with adequate resolution and linearity. A highernumber of bits produces a higher resolution amplitude component 106. Inone embodiment, amplitude correction module 110 may be implemented as adistortion correction or modification module to correct amplitudenon-linearity as a function of input amplitude (AM-AM) introduced intooutput signal 130 by power amplifier 128. AM-AM amplitude correctionmodule 110 may be configured as a pre-distortion module to correct fornon-linearity and distortion introduced by power amplifier 128 andtiming correction for circuit timing delays. The AM-AM pre-distortionamplitude correction module 110 digitally pre-distorts the inputamplitude using the input amplitude as the independent variable. Theembodiments are not limited in this context.

Phase component 108 may be provided to phase correction module 112.Output signal 114 of amplitude correction module 110 also may beprovided to phase correction module 112 to correct phase component 108for any distortion caused by amplitude modulation. In one embodiment,phase correction module 112 may be implemented as a distortioncorrection or modification module to correct for phase shift as afunction of input amplitude (AM-PM) introduced into output signal 130 bypower amplifier 128. AM-PM distortion correction module 112 may beconfigured as a pre-distortion module to correct for non-linearity anddistortion introduced by power amplifier 128 and timing corrections forcircuit timing delays. The AM-PM pre-distortion phase correction module112 digitally pre-distorts the input phase using the input phase as theindependent variable. Phase output signal 116 from phase correctionmodule 112 is provided to phase modulator 118. Phase modulated carriersignal 120 of phase modulator 118 is a phase modulated carrier and isprovided to a phase input port of power amplifier 128. The embodimentsare not limited in this context.

In one embodiment, power amplifier 128 may comprise 1-M amplificationstages, where M is any suitable number of amplification stages. In oneembodiment, power amplifier 128 may comprise three stages ofamplification. Bias driver 126 biases the first and second stages.Output signal 114 of amplitude correction module 110 is provided tosegment current driver 122. Segment current driver 122 drives the thirdstage of power amplifier 128 with amplitude modulation signal 124 tocontrol the digital envelope of each of the amplitude segments. Thethird amplification stage may comprise, for example, a HBT device.Amplitude modulation signal 124 may be applied to a base terminal of theHBT device in any suitable manner to implement one embodiment of basemodulation techniques previously described. For example, modulationsignal 124 may be applied to a transistor in series with the powersupply and the base terminal of the HBT device. Power amplifier 128combines phase modulated carrier signal 120 and amplitude modulationsignal 124 to construct a full complex waveform output signal 130 at anoutput terminal thereof. The embodiments are not limited in thiscontext.

FIG. 2 illustrates one embodiment of a polar modulated transmitter 200comprising a power amplifier 214 controlled using a suitable digitalbase modulation technique. Polar modulated transmitter 200 comprisessimilar digital correction and processing modules as described abovewith respect to FIG. 1. For example, data 102 is received and convertedby polar processing module 104. Amplitude component 106 is processed byAM-AM correction module 110 and phase component 108 is processed byAM-PM correction module 112 along with amplitude component 114. Phaseoutput signal 116 is provided to phase modulator 118. Phase modulatedcarrier signal 120 is provided to a phase input port of power amplifier214. The digital base modulation implementation for power amplifier 214is similar to that discussed above with respect to digital segmentedpower amplifier 128. One difference, however, is that at the finalcorrection stage of AM-AM correction module 110, the digital segmentcontrols of amplitude component 114 that otherwise would be applied to adigital segmented power amplifier, instead are applied to a basebanddigital-to-analog converter 202 (DAC). Analog signal 204 representativeof amplitude component 114 is provided to anti-alias filter 206 (AAF).AAF 206 smooths out analog signal 204 output of DAC 202 to compensatefor the non-linearity of the base modulation stage (e.g., third stage)of power amplifier 214. Filtered signal 208 is provided to base currentdriver 210. In various embodiments, output signal 204 or filtered signal208 may be coupled to a base terminal of a single HBT device at anoutput stage of power amplifier 214 to implement base modulationtechniques in a polar modulation environment. The embodiments are notlimited in this context.

In one embodiment, power amplifier 214 may comprise 1-M amplificationstages, where M is any suitable number of amplification stages. In oneembodiment, power amplifier 214 may comprise three stages ofamplification. Bias driver 126 biases the first and second stages.Current driver 210 drives the third stage of power amplifier 214 withamplitude modulation signal 212 to control the digital envelope of theamplitude signal. The third amplification stage may comprise, forexample, a HBT device. Amplitude modulation signal 212 may be applied toa base terminal of the HBT device in any suitable manner to implementone embodiment of base modulation techniques previously described. Poweramplifier 214 combines phase modulated carrier signal 120 and amplitudemodulation signal 212 to construct a full complex waveform output signal216 at an output terminal thereof. The embodiments are not limited inthis context.

Polar modulated transmitter 200 comprising power amplifier 214 may becontrolled using any suitable digital base modulation technique toimplement various wireless standards. For example, polar modulatedtransmitter 200 may be suitable in high linearity implementations.Accordingly, in one embodiment, a segmented stage of power amplifier 214may no longer be segmented, but rather may comprise a single large HBTdevice, for example. The HBT device may be driven by a single controlline with amplitude modulation signal 212. In base modulationimplementations, amplitude modulation signal 212 may be coupled to abase terminal of a single HBT device at an output stage of poweramplifier 214.

Controlling power amplifier 214 by driving HBT device over a singlecontrol line with amplitude modulation signal 212 enables severalimplementations of transmitter 200. These implementations may comprise,for example, an output signal 216 envelope resolution that is notlimited in by the physical number of segments in power amplifier 214.Rather, the resolution may be defined by the bit-widths designated indigital correction module 110, for example. In addition, there are nosmall time-domain transient effects in output signal 216 waveform due tosegment switching effects. This provides increased linearity and noiseperformance. Furthermore, reducing the number of segment control linesto a single control line simplifies the baseband filtering associatedwith a digital segmented power amplifier, for example. The embodiments,however, are not limited in this context.

The application of amplitude modulation signal 124, 212 to the baseterminal of a HBT device in both digital segmented power amplifier 128and power amplifier 214 supports a wide modulation bandwidth. In oneembodiment, these implementations may support modulation bandwidths ofseveral hundred MHz. Accordingly, the embodiments of transmitters 100,200 discussed above may be suitable for wideband applications such asWCDMA, for example. In other embodiments, extremely wide modulationbandwidth capability makes these control approaches suitable formulti-mode implementations of transmitters 100, 200, for example. Theembodiments, however, are not limited in this context.

It will appreciated that base modulation signals applied to the outputstages of amplifiers 128, 214 of respective polar architecture basedtransmitters 100, 200 are not limited to digitally processed waveformsand associated baseband DAC 202 output signals along the envelope oramplitude control path 220. Rather, the scope of the embodimentsdescribed herein is intended to cover the applications of analog controlwaveforms to a base terminal of the output stage of amplifiers 128, 214.For example, embodiments described herein cover the application of ananalog waveform to a base terminal of an HBT device in the output stageof amplifiers 128, 214 to implement the base modulation techniquedescribed herein.

FIG. 3 illustrates one embodiment of a polar modulated transmitter 300comprising power amplifier 214 controlled using any suitable digitalbase modulation technique. The architecture of polar modulatedtransmitter 300 is substantially similar to the architecture of polarmodulated transmitter 200 with the exception that the collector powersupply terminal of a transistor in the output stage of power amplifier214 is controlled by power converter 302. In one embodiment, powerconverter 302 may be a DC-DC converter. Power converter 302 may beselected via power control input signal 304. Power converter 302 iscoupled to a power supply voltage 306.

In general, use of power converter 302 on the collector supply terminalof a conventional power amplifier enables the collector voltage to beadjusted as a function of output power of amplifier 214. The efficiencyof power amplifier 214 may be optimized when the power amplifier 214 isbacked off from its maximum-rated power provided that power converter302 is efficient. This efficiency enhancement technique also may becompatible with digital base amplitude modulation techniques used tocontrol power amplifier 214. Accordingly, the combination of basemodulation and collector power supply control further optimizes theefficiency of power amplifier 214 under backed off conditions.

FIG. 4 illustrates one embodiment of a polar transmitter 400. Polartransmitter 400 comprises multiplying DAC 404. Digitally correctedamplitude information 402 is applied to input ports of multiplying DAC404. Digitally corrected amplitude information 402 may comprise 2-Mbits, where M represents any suitable number of bits to resolve theamplitude information with a suitable resolution and linearity.Digitally corrected amplitude information 402 may be received from anoutput port of AM-AM correction module, such as, for example, amplitudecorrection module 110. In one embodiment, multiplying or scaling controlsignal 406 may be provided to an input port of multiplying DAC 404.

In one embodiment, analog output signal 408 may be applied toanti-aliasing filter 410 (AAF). Filtered analog amplitude signal 412 isapplied to drivers 414 a, 414 b. Either driver 414 a, b may be selectedbased on a particular mode (e.g., high band mode or low band mode) ofoperation of transmitter 400. Depending on the particularimplementation, drivers 414 a, b each may comprise multiple voltage modeor current mode drivers to drive respective digital power amplifiers 418a, b. The number may be proportional to the number of amplificationstages of power amplifiers 418 a, b. For example, power amplifiers 418a, b may include P amplification stages biased by P drivers, where P isany number. At least one of the amplification stages may include atransistor device (e.g., HBT device) to receive a modulated signal at abase terminal thereof. Accordingly, at least one of the drivers 414 a, bmay be configured to provide the modulation signal to the base terminalof the output transistor device.

In one embodiment, drivers 414 a, b may be configured to operate in twoor more different modes. For example, in GSM EDGE implementations,drivers 414 a, b may be configured to drive both low band and high banddigital power amplifiers. Accordingly, driver 414 a may drive low bandpower amplifier 418 a bias output signals 416 a to provide suitablebiasing for each amplification stage of low band power amplifier 418 a.In addition, any one of bias output signals 416 a may include anamplitude modulation signal, e.g., amplitude modulation signal 212, tocontrol the digital envelope to be amplified by power amplifier 418 a.Driver 414 b may drive high band power amplifier 418 b bias outputsignals 416 b to provide suitable biasing for each amplification stageof power amplifier 418 b. In addition, any one of bias output signals416 b may include an amplitude modulation signal, e.g., amplitudemodulation signal 212, to control the digital envelope to be amplifiedby power amplifier 418 b. The amplitude modulation signal may be appliedto output amplification stages of power amplifiers 418 a, b. In oneembodiment, the amplitude modulation signal may be applied to a baseterminal of a HBT device in any suitable manner to implement oneembodiment of the base modulation techniques previously described.

In one embodiment, low band RF input signal 422 a RFin_(low) may beapplied to an input port of low band digital power amplifier 418 a. RFinput signal 422 a RFin_(low) comprises an RF carrier containing phasemodulation information. High band RF input signal 422 b RFin_(high) maybe applied to an input port of high band digital power amplifier 418 b.RF input signal 422 b also may comprise an RF carrier containing phasemodulation information. For example, signal 120 as discussed withrespect to FIGS. 1-3. Each digital power amplifier 418 a, b producesrespective amplified RF output signals 424 a, 424 b. RF output signals424 a, b include RF carrier, signal amplitude, and phase information.Digital power amplifiers 418 a, b are base modulated in at least oneamplification stage to produce output signals 424 a, b.

FIG. 5 illustrates one embodiment of a polar modulated transmitter 500comprising one embodiment of power amplifier 518 a including drivercircuit 514 a to drive bias currents and voltages to power amplifier 518a. Polar modulated transmitter 500 is a portion of a multi-modetransmitter where only the low band digital power amplifier portion isshown. Accordingly, in one embodiment of multi-mode polar modulatedtransmitter 500, power amplifier 518 a may be a low band digital poweramplifier. Power amplifier 518 a may be a RF DAC adapted fortelecommunications implementations. For example, in one embodiment,power amplifier 518 a may be adapted as a low band RF digital poweramplifier for GSM EDGE implementations. In one embodiment, poweramplifier 518 a comprises three amplification stages including a firstamplification stage 508 a, a second amplification stage 508 b, and athird amplification stage 508 c. Low band RF input signal 422 aRFin_(low) comprising an RF carrier containing phase modulationinformation may be applied to an input port of first amplification stage508 a. RF output signal 424 a may be applied to antenna or to otheramplification stages or circuit elements.

In one embodiment, driver 514 a comprises three bias modules 502 a, 502b, 502 c to drive respective bias currents or supply voltages 510 a, 510b, 510 c to bias respective amplification stages 508 a, 508 b, 508 c.Digitally corrected amplitude information 402 may be received from anoutput port of AM-AM correction module, such as, for example, amplitudecorrection module 110. In one embodiment, multiplying DAC 404 also mayreceive multiplying or scaling control signal 406 at an input port ofmultiplying DAC 404. In one embodiment, analog output signal 408 may beapplied to anti-aliasing filter 410 (AAF). As previously described, AAF410 smooths out analog signal 408 output of multiplying DAC 404 tocompensate for the non-linearity of third amplification stage 508 c(e.g., the base modulation stage) of power amplifier 518 a. Filteredanalog amplitude signal 412 of AAF 410 forms the input to each biasmodule 502 a-c. Bias modules 502 a-c may be configured to operate eitherin current mode or voltage mode to drive bias current or supply voltagein linear or non-linear (e.g., square) proportions. For example, biasmodule 502 a may be configured to operate in fast-linear current modeand bias modules 502 b, c may be configured to operate in linear voltagemode. In addition, each bias module 502 a-c may be configured toimplement analog shaping functions. At least one of bias modules 502 a-cmay be adapted to provide a modulation signal to a base terminal of atransistor in any one of amplification stages 508 a-c to implement abase modulation technique in accordance with the various embodimentsdescribed herein. For example, in one embodiment, bias module 508 c maybe configured to modulate a power amplifier transistor via a baseterminal of the transistor rather than a collector terminal. In oneembodiment, the amplifier transistor may be formed of GaAs HBTtechnology, for example, and bias module 508 c may be configured toprovide modulation signal 510 c to drive the base terminal of an HBTtransistor in third amplification stage 508 c (e.g., the output stage ofpower amplifier 518 a).

FIG. 6 illustrates one embodiment of a multi-mode polar transmitter 600.Multi-mode polar transmitter 600 comprises multiplying DAC 404.Digitally corrected amplitude information 402 is applied to input portsof multiplying DAC 404. Digitally corrected amplitude information 402may comprise 2-M bits, where M represents any suitable number of bits toresolve the amplitude information with a suitable resolution andlinearity. In one embodiment, digitally corrected amplitude information402 may be received from an output port of AM-AM correction module, suchas, for example, amplitude correction module 110.

In one embodiment, analog output signal 408 may be applied to AAF 410.Filtered analog amplitude signal 412 may be applied to mode selectswitch 602. Mode select switch 602 may be controlled via single knobcontrol signal 607. Mode select switch routes filtered analog amplitudesignal 412 to either low band or high digital power amplifiers 518 a or518 b, respectively. As previously discussed, in one embodiment, poweramplifier 518 a may be adapted as a low band RF digital power amplifierfor GSM EDGE implementations. Likewise, in one embodiment, poweramplifier 518 b may be adapted as a high band RF digital power amplifierfor GSM EDGE implementations. Accordingly, low band waveforms 412 a arerouted to low band digital power amplifier 518 a and high band waveforms412 b are routed to high band digital power amplifier 518 b thoroughrespective low band driver 614 a and high band driver 614 b based on theselection of single knob control signal 607. Either low band driver 614a or high band driver 614 b may be selected based on the particular modeof operation of transmitter 600 (e.g., high band mode or low band mode).Low band digital power amplifier 518 a receives input signal 422 a,which comprises and RF carrier containing phase information. High banddigital power amplifier 518 b receives input signal 422 b, whichcomprises and RF carrier containing phase information.

In one embodiment, low band driver 614 a may comprise multiple currentmode driver modules 612 a, 612 b, 612 c to bias respective bias cells608 a, 608 b, 608 c of low band digital power amplifier 518 aamplification stages 508 a, 508 b, 508 c, respectively. In oneembodiment, current mode driver modules 612 a-c may be configured toshape the analog waveforms of analog input signal 412 a. In oneembodiment, current mode driver modules 612 a-c supply bias currentI_(bias) to respective bias cells 608 a-c. Current mode driver module612 a generates bias current I_(bias1) to bias cell 608 a ofamplification stage 508 a. Current mode driver module 612 b generatesbias current I_(bias2) to bias cell 608 b of amplification stage 508 b.Current mode driver module 612 c generates bias current I_(bias3) tobias cell 608 c of amplification stage 508 c. In addition current modedriver module 612 c also generates modulation current signal I_(mod) tothe output stage of bias cell 608 c. I_(mod) represents amplitudemodulation signal based on digitally corrected amplitude information402. I_(mod) may be applied to the base terminal of an amplifiertransistor (e.g., HBT device) in amplification stage 508 c, for example.Detailed views of one embodiment of bias interfaces 7A and 7B are shownin FIGS. 7A and 7B.

In one embodiment, high band driver 614 b may comprise multiple currentmode driver modules 614 a, 614 b, 614 c to bias respective bias cells610 a, 610 b, 610 c of high band power amplifier 518 b amplificationstages 514 a, 514 b, 514 c, respectively. In operation high band driver614 a and power amplifier 518 a, including amplification stages 514 a-cand respective bias cells 610 a, 610 b, 610 c operate in a mannersimilar to that described above with respect to low band digital poweramplifier 518 a.

Output signals 424 a, b may be provided to an antenna for transmissionor may be provided to other circuit elements. Each output signal 424 a,b comprises RF carrier, amplitude, and phase information.

FIG. 7A illustrates one embodiment of a bias interface circuit for firstand second amplification stages 508 a, b and 514 a, b of respectivepower amplifiers 518 a, b. Bias interface circuit 700 represents oneembodiment of current mode driver modules 612 a, b, 614 a, b and biascells 608 a, b, 610 a, b. Bias interface circuit 700 may be configuredto drive bias currents I_(bias1) and I_(bias2) between current modedriver modules 612 a, 612 b formed on first substrate 702 and bias cells608 a, 608 b formed on second substrate 704. First substrate may beformed of Silicon (Si) and second substrate may be formed of GalliumArsenide (GaAs), for example.

In one embodiment, bias interface circuit 700 comprises current source706 to drive I_(bias) from current mode driver modules 612 a, b, 614 a,b to respective bias cells 608 a, b, 610 a, b. In one embodiment, biascells 608 a, b, 610 a, b comprise mirroring device 708 and RF device710. Mirroring device 708 drives I_(bias) in the output collector 712terminal of RF device 710. Both mirroring device 708 and RF device 710may be HBT devices.

FIG. 7B illustrates one embodiment of a bias interface circuit for thirdamplification stages 508 c, 514 c of respective power amplifiers 518 a,b. Bias interface circuit 750 represents one embodiment of current modedriver modules 612 c, 614 c and bias cells 608 c, 610 c. Bias interfacecircuit 750 may be configured to drive bias current I_(bias3) andmodulation current I_(mod) between current mode driver module 612 cformed on first substrate 702 and bias cell 608 c formed on secondsubstrate 704. As previously discussed, first substrate may be formed ofSi and second substrate may be formed of GaAs, for example.

In one embodiment, bias interface circuit 750 comprises current source756 to drive I_(bias3) from current mode driver module 612 c to biascell 608 c. In one embodiment, bias cell 608 c comprises mirroringdevice 758 and RF device 760. Mirroring device 758 drives I_(bias3) inthe output collector terminal 762 of RF device 760. Both mirroringdevice 758 and RF device 760 may be HBT devices. Modulation currentI_(mod) may be driven by transistor device 764 into base terminal 766 ofRF device 760. In one embodiment, transistor device 764 may be an N-MOSMOSFET transistor device. Collector terminal 762 is coupled to outputsof respective power amplifiers 518 a, b to generate respective amplifiedRF output signals 424 a, 424 b. As shown the base current of HBT device760 may be modulated by introducing N-MOS MOSFET transistor device 764in series with base terminal 766 of HBT device 760 and the power supply(e.g., battery), which delivers the required current at a controlledvoltage into base terminal 766 of HBT device 760. In this configuration,there is no voltage drop in the collector terminal of HBT device 760.Therefore, there is no degradation of the optimum efficiency that can beachieved relative to the situation where a MOS device. Furthermore, themodulation bandwidth that can be supported is not limited by thecapacitive loading associated with the large MOS device, and is notlimited by the closed-loop that is typically required to overcome thenon-linear characteristic of the MOS device.

FIG. 8 illustrates a graph 800 of a transfer characteristic of measuredAM-AM and AM-PM at high power without digital correction. Thecharacteristics are measured as function of base voltage applied to base766 of transistor 760. Horizontal axis 802 represents base voltage.First vertical axis 804 represents the magnitude of RF output voltage interms of voltage (e.g., 424 a, b) as a function of base 766 voltage.Second vertical axis 806 represents the phase of RF output voltage interms of degrees (e.g., 424 a, b) as a function of base 766 voltage.Magnitude of RF output voltage waveform 808 and phase of RF outputvoltage waveform 810 are shown as a function of base 766 voltage.

Operations for the above system and subsystem may be further describedwith reference to the following figures and accompanying examples. Someof the figures may include programming logic. Although such figurespresented herein may include a particular programming logic, it can beappreciated that the programming logic merely provides an example of howthe general functionality described herein can be implemented. Further,the given programming logic does not necessarily have to be executed inthe order presented unless otherwise indicated. In addition, the givenprogramming logic may be implemented by a hardware element, a softwareelement executed by a processor, or any combination thereof. Theembodiments are not limited in this context.

FIG. 9 illustrates one embodiment of a logic flow diagram 900.Accordingly, a power amplifier 518 a may be configured to receive (902)an amplitude signal 412 a of a polar modulated signal 402 at a baseterminal 766 of a transistor 760. Power amplifier 518 a receives (904) aphase modulated carrier signal 422 a of the polar modulated signal 402at the base terminal 766 of the transistor 760. Power amplifier 518 acombines (906) the amplitude signal 412 a and the phase modulated signal422 a to produce a full complex waveform 424 a at a collector terminal762 of the transistor 760.

In one embodiment, the amplitude signal 412 a may be pre-distorted byamplitude correction module 110 to compensate for non-linearity oftransistor 760. Further, the phase modulated carrier signal 422 a may bepre-distorted by phase correction module 112 to compensate fornon-linearity of the transistor 760.

In one embodiment, digital segment control signals may be received at aninput portion of a digital to analog converter and a polar modulatedsignal may be produced at an output portion of the digital to analogconverter.

In one embodiment, a power supply signal may be received by transistor764 and may be combined with the phase modulated carrier signal 422 aand the amplitude signal 412 a by transistor 760. The voltage at thecollector terminal 762 of the transistor 760 may be adjusted underbacked off conditions in accordance with output power of the transistor760.

For purposes of illustration, the above description has been provided inthe context of polar transmitter architectures. For instance, exampleshave been provided that involve HBT-based power amplifiers. However, theembodiments are not limited to HBT or any type of Bi-Polar transistor.In fact, other transistor technologies may be used.

For instance, embodiments may employ field effect transistor (FET)technology. For such embodiments, FETs may be substituted for bi-polartransistors. Moreover, connections to FET gate terminals may besubstituted for connections to bi-polar transistor base terminals. Also,connections to FET drain terminals may be substituted for connectionsbi-polar transistor collector terminals.

Examples of such substitutions are provided in FIGS. 10A and 10B. Thesedrawings, like FIGS. 7A and 7B, illustrate exemplary bias interfacecircuits. However, instead of employing bipolar HBTs, the circuits ofFIGS. 10A and 10B employ FETs.

In particular, FIG. 10A illustrates one embodiment of a bias interfacecircuit 1000 for first and second amplification stages 508 a, b and 514a, b of respective power amplifiers 518 a, b. Bias interface circuit1000 represents one embodiment of current mode driver modules 612 a, b,614 a, b and bias cells 608 a, b, 610 a, b. Bias interface circuit 1000may be configured to drive bias currents I_(bias1) and I_(bias2) betweencurrent mode driver modules 612 a, 612 b formed on first substrate 1002and bias cells 608 a, 608 b formed on second substrate 1004. Firstsubstrate may be formed of Silicon (Si) and second substrate may beformed of Gallium Arsenide (GaAs), for example. However, the embodimentsare not limited to this example.

In one embodiment, bias interface circuit 1000 comprises current source1006 to drive I_(bias) from current mode driver modules 612 a, b, 614 a,b to respective bias cells 608 a, b, 610 a, b. In one embodiment, biascells 608 a, b, 610 a, b comprise mirroring device 1008 and RF device1010. Mirroring device 1008 drives I_(bias) in the output drain 1012terminal of RF device 1010. Both mirroring device 1008 and RF device1010 may be FET devices.

FIG. 10B illustrates one embodiment of a bias interface circuit 1050 forthird amplification stages 508 c, 514 c of respective power amplifiers518 a, b. Bias interface circuit 1050 represents one embodiment ofcurrent mode driver modules 612 c, 614 c and bias cells 608 c, 610 c.Bias interface circuit 1050 may be configured to drive bias currentI_(bias3) and modulation current I_(mod) between current mode drivermodule 612 c formed on first substrate 1002 and bias cell 608 c formedon second substrate 1004. As previously discussed, first substrate maybe formed of Si and second substrate may be formed of GaAs, for example.However, other substrate types may be employed.

In one embodiment, bias interface circuit 1050 comprises current source1056 to drive I_(bias3) from current mode driver module 612 c to biascell 608 c. In one embodiment, bias cell 608 c comprises mirroringdevice 1058 and RF device 1060. Mirroring device 1058 drives I_(bias3)in the output drain terminal 1062 of RF device 1060. Both mirroringdevice 1058 and RF device 1060 may be FET devices. Modulation currentI_(mod) may be driven by transistor device 1064 into gate terminal 1066of RF device 1060. In one embodiment, transistor device 1064 may be anN-MOS MOSFET transistor device. Drain terminal 1062 is coupled tooutputs of respective power amplifiers 518 a, b to generate respectiveamplified RF output signals 424 a, 424 b. As shown the gate current ofFET device 1060 may be modulated by introducing N-MOS MOSFET transistordevice 1064 in series with gate terminal 1066 of FET device 1060 and thepower supply (e.g., battery), which delivers the required current at acontrolled voltage into gate terminal 1066 of FET device 1060. In thisconfiguration, there is no voltage drop in the drain terminal of FETdevice 1060. Therefore, there is no degradation of the optimumefficiency that can be achieved relative to the situation where a MOSdevice. Furthermore, the modulation bandwidth that can be supported isnot limited by the capacitive loading associated with the large MOSdevice, and is not limited by the closed-loop that is typically requiredto overcome the non-linear characteristic of the MOS device.

The disclosure herein provides various examples involving modulation.Some of these examples involve three stages, in which base/gatemodulation is performed at a third stage. However, it is important tonote that various numbers of stages may be employed. Also, gate and/orbase modulation, as described herein, may be performed and implementedat any one of such stages. Moreover, gate and/or base modulation may beperformed and implemented at any combination of two or more such stages.Thus, the embodiments are not limited to the examples provided herein.Moreover, techniques described herein may be employed with polarmodulation as well as other modulation types.

Numerous specific details have been set forth herein to provide athorough understanding of the embodiments. It will be understood bythose skilled in the art, however, that the embodiments may be practicedwithout these specific details. In other instances, well-knownoperations, components and circuits have not been described in detail soas not to obscure the embodiments. It can be appreciated that thespecific structural and functional details disclosed herein may berepresentative and do not necessarily limit the scope of theembodiments.

It is also worthy to note that any reference to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. The appearances of the phrase “in oneembodiment” in various places in the specification are not necessarilyall referring to the same embodiment.

Some embodiments may be implemented using an architecture that may varyin accordance with any number of factors, such as desired speed, powerlevels, heat tolerances, semiconductor manufacturing processing, inputrates, output rates, memory resources, and other performanceconstraints.

Some embodiments may be described using the expression “coupled” alongwith their derivatives. It should be understood that the term “coupled”may be used to indicate that two or more elements are in direct physicalor electrical contact. The term “coupled,” however, also may mean thattwo or more elements are not in direct contact with each other, but yetstill co-operate or interact with each other. The embodiments are notlimited in this context.

While certain features of the embodiments have been illustrated asdescribed herein, many modifications, substitutions, changes andequivalents will now occur to those skilled in the art. It is thereforeto be understood that the appended claims are intended to cover all suchmodifications and changes as fall within the true spirit of theembodiments.

1. A method, comprising: receiving an amplitude signal of a polarmodulated signal at a gate terminal of a transistor; receiving a phasemodulated carrier signal of said polar modulated signal at said gateterminal of said transistor; and combining said amplitude signal andsaid phase modulated signal to produce a full complex waveform at adrain terminal of said transistor.
 2. The method of claim 1, comprisingpre-distorting said amplitude signal to compensate for non-linearity ofsaid transistor.
 3. The method of claim 1, comprising pre-distortingsaid phase modulated carrier signal to compensate for non-linearity ofsaid transistor.
 4. The method of claim 1, comprising: receiving digitalsegment control signals at an input portion of a digital to analogconverter; and producing said polar modulated signal at an outputportion of said digital to analog converter.
 5. The method of claim 1,comprising: receiving a power supply signal; and combining said phasemodulated carrier signal and said amplitude signal with said powersupply signal.
 6. The method of claim 5, comprising: adjusting a voltageat a drain terminal of said transistor under backed off conditions inaccordance with output power of said transistor.
 7. An apparatus,comprising: a first amplifier to receive a first amplitude signal of apolar modulated signal at a gate terminal of a first transistor; toreceive a first phase modulated carrier signal of said polar modulatedsignal at said gate terminal of said first transistor; and to combinesaid first amplitude signal and said first phase modulated signal toproduce a first full complex waveform at a drain terminal of said firsttransistor.
 8. The apparatus of claim 7, comprising an amplitudecorrection module to pre-distort said amplitude signal to compensate fornon-linearity of said transistor.
 9. The apparatus of claim 7,comprising a phase correction module to pre-distort said first phasemodulated carrier signal to compensate for non-linearity of said firsttransistor.
 10. The apparatus of claim 7, comprising a digital to analogconverter to receive digital segment control signals at an input portionto produce said polar modulated signal at an output portion of saiddigital to analog converter.
 11. The apparatus of claim 7, comprising aninterface module to receive a power supply signal and to combine saidfirst phase modulated carrier signal and said first amplitude signalwith said power supply signal.
 12. The apparatus of claim 11, whereinsaid interface module is to adjust a voltage at a drain terminal of saidfirst transistor under backed off conditions in accordance with outputpower of said first transistor.
 13. The apparatus of claim 7,comprising: a second amplifier to receive a second amplitude signal ofsaid polar modulated signal at a gate terminal of a second transistor;to receive a second phase modulated carrier signal of said polarmodulated signal at said gate terminal of said second transistor; and tocombine said second amplitude signal and said second phase modulatedsignal to produce a second full complex waveform at a drain terminal ofsaid second transistor.
 14. The apparatus of claim 13, comprising a modeselect switch to select either said first amplifier or said secondamplifier.
 15. An system, comprising: a first antenna; and a firstamplifier coupled to said first antenna, said first amplifier to receivea first amplitude signal of a polar modulated signal at a gate terminalof a first transistor; to receive a first phase modulated carrier signalof said polar modulated signal at said gate terminal of said firsttransistor; and to combine said first amplitude signal and said firstphase modulated signal to produce a first full complex waveform at adrain terminal of said first transistor.
 16. The system of claim 15,comprising an amplitude correction module to pre-distort said amplitudesignal to compensate for non-linearity of said transistor.
 17. Thesystem of claim 15, comprising a phase correction module to pre-distortsaid first phase modulated carrier signal to compensate fornon-linearity of said first transistor.
 18. The system of claim 15,comprising a digital to analog converter to receive digital segmentcontrol signals at an input portion to produce said polar modulatedsignal at an output portion of said digital to analog converter.
 19. Thesystem of claim 15, comprising an interface module to receive a powersupply signal and to combine said first phase modulated carrier signaland said first amplitude signal with said power supply signal.
 20. Thesystem of claim 19, wherein said interface module is to adjust a voltageat a drain terminal of said first transistor under backed off conditionsin accordance with output power of said first transistor.
 21. The systemof claim 15, comprising: a second antenna; and a second amplifiercoupled to said second antenna, said second amplifier to receive asecond amplitude signal of said polar modulated signal at a gateterminal of a second transistor; to receive a second phase modulatedcarrier signal of said polar modulated signal at said gate terminal ofsaid second transistor; and to combine said second amplitude signal andsaid second phase modulated signal to produce a second full complexwaveform at a drain terminal of said second transistor.
 22. The systemof claim 21, comprising a mode select switch to select either said firstamplifier or said second amplifier.